Based on 3D process and device simulations with mechanical stress simulations by finite element techniques, this book explains performance assessment of nanoscale devices with strained SiGe and other stressors. It explains the process-induced stress transfer and developments at 7nm technology and below node in the area of strain-engineered devices.
Anticipating a limit to the continuous miniaturization (More-Moore), intense research efforts are being made to co-integrate various functionalities (More-than-Moore) in a single chip. Currently, strain engineering is the main technique used to enhance the performance of advanced semiconductor devices. Written from an engineering applications standpoint, this book encompasses broad areas of semiconductor devices involving the design, simulation, and analysis of Si, heterostructure silicongermanium (SiGe), and III-N compound semiconductor devices. The book provides the background and physical insight needed to understand the new and future developments in the technology CAD (TCAD) design at the nanoscale.
Features
This book is for graduate students and researchers studying solid-state devices and materials, microelectronics, systems and controls, power electronics, nanomaterials, and electronic materials and devices.